Ð þí¥Œ8›€( ›H rockchip,px30-evbrockchip,px30 +7Rockchip PX30 EVBaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000ƒ/serial@ff178000‹/spi@ff1d0000�/spi@ff1d8000cpus+cpu@0•cpuarm,cortex-a35¡¥psci³ºÉÙZócpu@1•cpuarm,cortex-a35¡¥psci³ºÉÙZócpu@2•cpuarm,cortex-a35¡¥psci³ºÉÙZó cpu@3•cpuarm,cortex-a35¡¥psci³ºÉÙZó idle-statespscicpu-sleeparm,idle-state'8Ox`úp„cluster-sleeparm,idle-state'8O�`ôpÐcpu0-opp-tableoperating-points-v2�opp-600000000Œ#ÃF “~ð~ð™p¡œ@²opp-816000000Œ0£, “��™p¡œ@opp-1008000000Œ<Ü “íØíØ™p¡œ@opp-1200000000ŒG†Œ “Ö Ö ™p¡œ@opp-1296000000ŒM?d “™p™p™p¡œ@arm-pmuarm,cortex-a35-pmu0¾defgÉ display-subsystemrockchip,display-subsystemÜ âokayexternal-gmac-clock fixed-clockéúð€ ùgmac_clkin psci arm,psci-1.0¬smctimerarm,armv8-timer0¾   thermal-zonessoc-thermal/è=îO tripstrip-point-0_pkМpassivetrip-point-1_LkМpassivesoc-crit_Á8kÐ œcriticalcooling-mapsmap0v {ÿÿÿÿÿÿÿÿŠmap1v {ÿÿÿÿÿÿÿÿŠgpu-thermald/èO xin24m fixed-clock én6ùxin24mapower-management@ff000000$rockchip,px30-pmusysconsimple-mfd¡ÿpower-controllerrockchip,px30-power-controller—+cpd_usb@5¡³<«pd_sdcard@7¡³÷;«pd_gmac@9¡  ³²C@?«pd_mmc_nand@10¡ @³þÿ978:«pd_vpu@11¡ ³¯ôK«pd_vo@12¡ X³·µ¶–—ýûüD56«pd_vi@13¡ (³³´ùú3« !"pd_gpu@14¡³I«#syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd¡ÿ+‚io-domains$rockchip,px30-pmu-io-voltage-domainâokay²$À$reboot-modesyscon-reboot-modeÎÕRBÃåRBà óRBÃÿRBà RBÃserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart¡ÿ ¾³%%baudclkapb_pclk%&&*txrx4>Kdefault Y'() âdisabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s¡ÿ ¾ ³i2s_clki2s_hclk%&&*txrxKdefaultY*+,-câokayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s¡ÿ ¾³i2s_clki2s_hclk%&&*txrxKdefaultY./01c âdisabledinterrupt-controller@ff131000 arm,gic-400t…@¡ÿÿ ÿ@ ÿ`  ¾ syscon@ff140000$rockchip,px30-grfsysconsimple-mfd¡ÿ+6io-domains rockchip,px30-io-voltage-domainâokayš2¨3¶4Ä$Ò4à2lvdsrockchip,px30-lvdsî5ódphyý6 lvds âdisabledports+port@0¡+endpoint@0¡7~endpoint@1¡8�serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart¡ÿ€ ¾³Ibaudclkapb_pclk%&&*txrx4>KdefaultY9:âokayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart¡ÿ ¾³Jbaudclkapb_pclk%&&*txrx4>KdefaultY; âdisabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart¡ÿ€ ¾³Kbaudclkapb_pclk%&&*txrx4>Kdefault Y<=> âdisabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart¡ÿ ¾³Lbaudclkapb_pclk%&& *txrx4>Kdefault Y?@A âdisabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart¡ÿ€ ¾³Mbaudclkapb_pclk%& & *txrx4>Kdefault YBCDâokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2c¡ÿ³N i2cpclk ¾KdefaultYE+âokaypmic@20rockchip,rk809¡  F¾KdefaultYG*K ùxin32kYHeHqH}H‰I•I¡I­I¹HregulatorsDCDC_REG1Åvdd_logÔ~ðì™pq-vregulator-state-mem?W~ðDCDC_REG2Åvdd_armÔ~ðì™pq-regulator-state-memsW~ðDCDC_REG3Åvcc_ddr-regulator-state-mem?DCDC_REG4Åvcc_3v0Ô-ÆÀì-ÆÀ-4regulator-state-mem?W-ÆÀDCDC_REG5 Åvcc3v3_sysÔ2Z ì2Z -Iregulator-state-mem?W2Z LDO_REG1Åvcc_1v0ÔB@ìB@-regulator-state-mem?WB@LDO_REG2Åvcc_1v8Ôw@ìw@-2regulator-state-mem?Ww@LDO_REG3Åvdd_1v0ÔB@ìB@-regulator-state-mem?WB@LDO_REG4 Åvcc3v0_pmuÔ-ÆÀì-ÆÀ-$regulator-state-mem?W-ÆÀLDO_REG5 Åvccio_sdÔw@ì2Z -3regulator-state-mem?W2Z LDO_REG6Åvcc_sdÔ2Z ì2Z -mregulator-state-mem?W2Z LDO_REG7 Åvcc2v8_dvpÔ*¹€ì*¹€-regulator-state-memsW*¹€LDO_REG8 Åvcc1v8_dvpÔw@ìw@-regulator-state-mem?Ww@LDO_REG9 Åvcc1v5_dvpÔã`ìã`-regulator-state-memsWã`SWITCH_REG1 Åvcc3v3_lcd-KSWITCH_REG2 Åvcc5v0_host-i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2c¡ÿ³O i2cpclk ¾KdefaultYJ+âokaysensor@dasahi-kasei,ak8963¡  ŒF’$�100010001touchscreen@14goodix,gt1151¡ F¾ ªF ´F ÀKsensor@4c fsl,mma7660¡L F¾i2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2c¡ÿ³P i2cpclk ¾ KdefaultYL+ âdisabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c¡ÿ³ Q i2cpclk ¾ KdefaultYM+ âdisabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi¡ÿ ¾³$Uspiclkapb_pclk%& & *txrxKdefaultYNOPQ+ âdisabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi¡ÿ€ ¾³%Vspiclkapb_pclk%&&*txrxKdefaultYRSTUV+ âdisabledwatchdog@ff1e0000 snps,dw-wdt¡ÿ³[ ¾% âdisabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ ³"S pwmpclkKdefaultYWÍ âdisabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ ³"S pwmpclkKdefaultYXÍâokay�pwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ ³"S pwmpclkKdefaultYYÍ âdisabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ 0³"S pwmpclkKdefaultYZÍ âdisabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ €³#T pwmpclkKdefaultY[Í âdisabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ €³#T pwmpclkKdefaultY\Í âdisabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ € ³#T pwmpclkKdefaultY]Í âdisabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm¡ÿ €0³#T pwmpclkKdefaultY^Í âdisabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer¡ÿ! ¾³Y& pclktimerbus simple-bus+Ødmac@ff240000arm,pl330arm,primecell¡ÿ$@¾ß³» apb_pclkö&tsadc@ff280000rockchip,px30-tsadc¡ÿ( ¾$,ÃP³,Xtsadcapb_pclk&¨ -tsadc-apbý69ÔÀKinitdefaultsleepY_P`Z_dâokayz‘ saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc¡ÿ(€ ¾T¬³-Wsaradcapb_pclk&¥ -saradc-apbâokay¾2Žnvmem@ff290000rockchip,px30-otp¡ÿ)@³/Zaotpapb_pclkphy&´-phy+id@7¡cpu-leakage@17¡performance@1e¡Êclock-controller@ff2b0000rockchip,px30-cru¡ÿ+ ³a% xin24mgpllý6 Ï8«°ðõ@IFÏq ë ëÂðÑ€ðÑ€õá ëÂclock-controller@ff2bc000rockchip,px30-pmucru¡ÿ+À³axin24mý6 Ï%%% G†Œõጺ€%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd¡ÿ,+usb2-phy@100rockchip,px30-usb2phy¡ ³% phyclk Üb ùusb480m_phyâokaybhost-portó ¾D þlinestateâokayeotg-portó$¾BA@þotg-bvalidotg-idlinestateâokaydphy@ff2e0000rockchip,px30-dsi-dphy¡ÿ.³% E refpclk&>-apbóc âokay5usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc2¡ÿ0 ¾>³otgotg$6E€€@ îd óusb2-phycâokayusb@ff340000 generic-ehci¡ÿ4 ¾<³îeóusbcâokayusb@ff350000 generic-ohci¡ÿ5 ¾=³îeóusbcâokayethernet@ff360000rockchip,px30-gmac¡ÿ6 ¾+þmacirq@³>??@A²CL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedý6TrmiiKdefaultYfgc &^ -stmmacethâokay]outputj4 uh … ›ÃPÃPmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc¡ÿ7@ ¾6 ³÷;CDbiuciuciu-driveciu-sample°ºÅðÑ€KdefaultYijklcâokayÓåö "/=mI3mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc¡ÿ8@ ¾7 ³ÿ8EFbiuciuciu-driveciu-sample°ºÅðÑ€Kdefault Ynopc âokayåVlzq/mmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc¡ÿ9@ ¾5 ³9GHbiuciuciu-driveciu-sample°ºÅðÑ€Kdefault Yrstc âokayÓ…lzu=4I2gpu@ff400000$rockchip,px30-maliarm,mali-bifrost¡ÿ@@$¾/.- þjobmmugpu³Iºcâokay”vdsi@ff450000rockchip,px30-mipi-dsi¡ÿE ¾K³Dpclkî5ódphyc &=-apbý6+âokayports+port@0¡+endpoint@0¡w}endpoint@1¡x€port@1¡endpointy{panel@0xinpeng,xpp055c272¡ zª2·Kportendpoint{yvop@ff460000rockchip,px30-vop-big¡ÿFü ¾M³µ–ûaclk_vopdclk_vophclk_vop&345 -axiahbdclkÂ|c âokayport+ endpoint@0¡}wendpoint@1¡~7iommu@ff460f00rockchip,iommu¡ÿF ¾M þvopb_mmu³µû aclkifacec Éâokay|vop@ff470000rockchip,px30-vop-lit¡ÿGü ¾N³¶—üaclk_vopdclk_vophclk_vop&789 -axiahbdclkÂc âokayport+ endpoint@0¡€xendpoint@1¡�8iommu@ff470f00rockchip,iommu¡ÿG ¾N þvopl_mmu³¶ü aclkifacec Éâokayqos@ff518000syscon¡ÿQ€ qos@ff520000syscon¡ÿR #qos@ff52c000syscon¡ÿRÀ qos@ff538000syscon¡ÿS€ qos@ff538080syscon¡ÿS€€ qos@ff538100syscon¡ÿS� qos@ff538180syscon¡ÿS�€ qos@ff540000syscon¡ÿT qos@ff540080syscon¡ÿT€ qos@ff548000syscon¡ÿT€ qos@ff548080syscon¡ÿT€€ qos@ff548100syscon¡ÿT�  qos@ff548180syscon¡ÿT�€ !qos@ff548200syscon¡ÿT‚ "qos@ff550000syscon¡ÿU qos@ff550080syscon¡ÿU€ qos@ff550100syscon¡ÿU qos@ff550180syscon¡ÿU€ qos@ff558000syscon¡ÿU€ qos@ff558080syscon¡ÿU€€ pinctrlrockchip,px30-pinctrlý6Ö‚+Øgpio0@ff040000rockchip,gpio-bank¡ÿ ¾³%ãó…tFgpio1@ff250000rockchip,gpio-bank¡ÿ% ¾³\ãó…t‘gpio2@ff260000rockchip,gpio-bank¡ÿ& ¾³]ãó…thgpio3@ff270000rockchip,gpio-bank¡ÿ' ¾³^ãó…tpcfg-pull-upÿ…pcfg-pull-down Œpcfg-pull-none „pcfg-pull-none-2ma  (pcfg-pull-up-2maÿ (pcfg-pull-up-4maÿ (†pcfg-pull-none-4ma  (pcfg-pull-down-4ma  (pcfg-pull-none-8ma  (‰pcfg-pull-up-8maÿ (‡pcfg-pull-none-12ma  ( ‹pcfg-pull-up-12maÿ ( Špcfg-pull-none-smt  7ƒpcfg-output-high Lpcfg-output-low X�pcfg-input-highÿ cˆpcfg-input ci2c0i2c0-xfer pƒ ƒEi2c1i2c1-xfer pƒƒJi2c2i2c2-xfer pƒƒLi2c3i2c3-xfer p ƒ ƒMtsadctsadc-otp-pin p„_tsadc-otp-out p„`uart0uart0-xfer p … …'uart0-cts p „(uart0-rts p „)uart1uart1-xfer p……9uart1-cts p„:uart1-rts p„uart2-m0uart2m0-xfer p……;uart2-m1uart2m1-xfer p ……uart3-m0uart3m0-xfer p……uart3m0-cts p„uart3m0-rts p„uart3-m1uart3m1-xfer p……<uart3m1-cts p „=uart3m1-rts p „>uart4uart4-xfer p……?uart4-cts p„@uart4-rts p„Auart5uart5-xfer p……Buart5-cts p„Cuart5-rts p„Dspi0spi0-clk p†Nspi0-csn p†Ospi0-miso p †Pspi0-mosi p †Qspi0-clk-hs p‡spi0-miso-hs p ‡spi0-mosi-hs p ‡spi1spi1-clk p†Rspi1-csn0 p †Sspi1-csn1 p †Tspi1-miso p†Uspi1-mosi p †Vspi1-clk-hs p‡spi1-miso-hs p‡spi1-mosi-hs p ‡pdmpdm-clk0m0 p„pdm-clk0m1 p„pdm-clk1 p„pdm-sdi0m0 p„pdm-sdi0m1 p„pdm-sdi1 p„pdm-sdi2 p„pdm-sdi3 p„pdm-clk0m0-sleep pˆpdm-clk0m1-sleep pˆpdm-clk1-sleep pˆpdm-sdi0m0-sleep pˆpdm-sdi0m1-sleep pˆpdm-sdi1-sleep pˆpdm-sdi2-sleep pˆpdm-sdi3-sleep pˆi2s0i2s0-8ch-mclk p„i2s0-8ch-sclktx p„i2s0-8ch-sclkrx p „i2s0-8ch-lrcktx p„i2s0-8ch-lrckrx p „i2s0-8ch-sdo0 p„i2s0-8ch-sdo1 p„i2s0-8ch-sdo2 p„i2s0-8ch-sdo3 p„i2s0-8ch-sdi0 p„i2s0-8ch-sdi1 p „i2s0-8ch-sdi2 p „i2s0-8ch-sdi3 p„i2s1i2s1-2ch-mclk p„i2s1-2ch-sclk p„*i2s1-2ch-lrck p„+i2s1-2ch-sdi p„,i2s1-2ch-sdo p„-i2s2i2s2-2ch-mclk p„i2s2-2ch-sclk p„.i2s2-2ch-lrck p„/i2s2-2ch-sdi p„0i2s2-2ch-sdo p„1sdmmcsdmmc-clk p‰isdmmc-cmd p‡jsdmmc-det p‡ksdmmc-bus1 p‡sdmmc-bus4@ p‡‡‡‡lsdiosdio-clk p„psdio-cmd p…osdio-bus4@ p…………nemmcemmc-clk p ‰remmc-cmd p ‡semmc-rstnout p „emmc-bus1 p‡emmc-bus4@ p‡‡‡‡emmc-bus8€ p‡‡‡‡‡‡‡‡temmc-reset p „�flashflash-cs0 p„flash-rdy p „flash-dqs p „flash-ale p „flash-cle p „flash-wrn p „flash-csl p„flash-rdn p„flash-bus8€ pŠŠŠŠŠŠŠŠlcdclcdc-rgb-dclk-pin p‹lcdc-rgb-m0-hsync-pin p‹lcdc-rgb-m0-vsync-pin p‹lcdc-rgb-m0-den-pin p‹lcdc-rgb888-m0-data-pins€ p‰‰‰‰ ‰ ‰ ‰‰‰‰ ‰ ‰‰‰‰‰‰‰‰‰‰‰‰‰lcdc-rgb666-m0-data-pins p‰‰‰‰ ‰ ‰ ‰‰‰‰ ‰ ‰‰‰‰‰‰‰lcdc-rgb565-m0-data-pins p‰‰‰‰ ‰ ‰ ‰‰‰‰ ‰ ‰‰‰‰‰lcdc-rgb888-m1-data-pins p‰‰ ‰ ‰ ‰‰‰‰‰‰‰‰‰‰‰‰‰lcdc-rgb666-m1-data-pins° p‰‰ ‰ ‰ ‰‰‰‰‰‰‰lcdc-rgb565-m1-data-pins� p‰‰ ‰ ‰ ‰‰‰‰‰pwm0pwm0-pin p„Wpwm1pwm1-pin p„Xpwm2pwm2-pin p „Ypwm3pwm3-pin p„Zpwm4pwm4-pin p„[pwm5pwm5-pin p„\pwm6pwm6-pin p„]pwm7pwm7-pin p„^gmacrmii-pins� p‹‹‹„„„„„ „fmac-refclk-12ma p ‹gmac-refclk p „cif-m0cif-clkout-m0 p „dvp-d2d9-m0À p„„„„„„„„„ „ „ „dvp-d0d1-m0 p „„d10-d11-m0 p„„cif-m1cif-clkout-m1 p„dvp-d2d9-m1À p„„„„ „ „„„„„„„dvp-d0d1-m1 p„„d10-d11-m1 p„„ispisp-prelight p„headphonehp-det pŒpmicpmic_int p…Gsoc_slppin_gpio p�soc_slppin_slp p„soc_slppin_rst p„sdio-pwrseqwifi-enable-h p„’chosen ~serial5:115200n8adc-keys adc-keys ŠŽ –buttons §w@ Ádesc-key Ïesc Õ àý0home-key Ïhome Õf à …€menu-key Ïmenu Õ‹ àxvol-down-key Ïvolume down Õr à“àvol-up-key Ïvolume up Õs àBhbacklightpwm-backlight ú�a¨ ÿKzemmc-pwrseqmmc-pwrseq-emmcY�Kdefault ´‘ usdio-pwrseqmmc-pwrseq-simpleKdefaultY’ ´Fqvccsysregulator-fixed Åvcc5v0_sys-ÔLK@ìLK@H compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendgpiosvdd-supplymount-matrixirq-gpiosreset-gpiosVDDIO-supply#pwm-cellsrangesarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8vmali-supplybacklightiovcc-supplyvci-supplyiommus#iommu-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpwmspower-supply