mips_cpu_types.h File Reference

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Macros
mips_cpu_types.h File Reference
#include <misc.h>
#include "thirdparty/mips_cpuregs.h"

Go to the source code of this file.

Macros

#define EXC3K   3
 
#define EXC4K   4
 
#define EXC32   32
 
#define EXC64   64
 
#define MMU3K   3
 
#define MMU4K   4
 
#define MMU8K   8
 
#define MMU10K   10
 
#define MMU32   32
 
#define MMU64   64
 
#define NOLLSC   1
 
#define DCOUNT   2
 
#define NOFPU   4
 
#define MIPS_CPU_TYPE_DEFS
 

Macro Definition Documentation

◆ DCOUNT

#define DCOUNT   2

Definition at line 53 of file mips_cpu_types.h.

◆ EXC32

#define EXC32   32

Definition at line 41 of file mips_cpu_types.h.

◆ EXC3K

#define EXC3K   3

Definition at line 39 of file mips_cpu_types.h.

Referenced by cop0_availability_check(), coproc_tlbwri(), and X().

◆ EXC4K

#define EXC4K   4

Definition at line 40 of file mips_cpu_types.h.

◆ EXC64

#define EXC64   64

Definition at line 42 of file mips_cpu_types.h.

◆ MIPS_CPU_TYPE_DEFS

#define MIPS_CPU_TYPE_DEFS
Value:
{ \
{ "R2000", MIPS_R2000, 0x00, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \
{ "R2000A", MIPS_R2000, 0x10, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \
{ "R3000", MIPS_R3000, 0x20, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,12,2,1,12,2,1, 0, 0, 0 }, \
{ "R3000A", MIPS_R3000, 0x30, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \
{ "R6000", MIPS_R6000, 0x00, 0, EXC3K, MMU3K, 2, 0, 32, 1,16,2,2,16,2,2, 0, 0, 0 }, /* instrs/cycle? */ \
{ "R4000", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2,13,4,2,13,4,2,19, 6, 1 }, \
{ "R4000PC", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2,13,4,2,13,4,2, 0, 6, 1 }, \
{ "R10000", MIPS_R10000,0x26, 0, EXC4K, MMU10K, 4, 0, 64, 4,15,6,2,15,5,2,20, 6, 1 }, \
{ "R4200", MIPS_R4200, 0x00, 0, EXC4K, MMU4K, 3, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
{ "R4300", MIPS_R4300, 0x00, 0, EXC4K, MMU4K, 3, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
{ "R4100", MIPS_R4100, 0x00, 0, EXC4K, MMU4K, 3, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
{ "VR4102", MIPS_R4100, 0x40, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,12,0,0,10,0,0, 0, 0, 0 }, /* TODO: Bogus? */ \
{ "VR4181", MIPS_R4100, 0x50, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,14,4,0,13,4,0, 0, 0, 0 }, \
{ "VR4121", MIPS_R4100, 0x60, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,14,4,0,13,4,0, 0, 0, 0 }, \
{ "VR4122", MIPS_R4100, 0x70, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,15,5,0,14,4,0, 0, 0, 0 }, \
{ "VR4131", MIPS_R4100, 0x80, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,14,5,0,14,5,0, 0, 0, 0 }, \
{ "R4400", MIPS_R4000, 0x40, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2,14,4,1,14,4,1,20, 6, 1 }, \
{ "R4600", MIPS_R4600, 0x00, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ "R4700", MIPS_R4700, 0x00, 0, EXC4K, MMU4K, 3, 0, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
{ "R4650", MIPS_R4650, 0x00, 0, EXC4K, MMU4K, 3, 0, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \
{ "R8000", MIPS_R8000, 0, 0, EXC4K, MMU8K, 4, 0, 192, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* 192 tlb entries? or 384? instrs/cycle? */ \
{ "R12000", MIPS_R12000,0x23, 0, EXC4K, MMU10K, 4, 0, 64, 4,15,6,2,15,5,2,23, 6, 1 }, \
{ "R14000", MIPS_R14000,0, 0, EXC4K, MMU10K, 4, 0, 64, 4,15,6,2,15,5,2,22, 6, 1 }, \
{ "R5000", MIPS_R5000, 0x21, DCOUNT, EXC4K, MMU4K, 4, 0, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* 2way I,D; instrs/cycle? */ \
{ "R5900", MIPS_R5900, 0x20, 0, EXC4K, MMU4K, 3, 0, 48, 4,14,6,2,13,6,2, 0, 0, 0 }, /* instrs/cycle? */ \
{ "TX3920", MIPS_TX3900,0x30, 0, EXC32, MMU32, 1, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \
{ "TX7901", MIPS_TX7900,0x01, 0, EXC4K, MMU4K, 3, 1, 48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \
{ "VR5432", MIPS_R5400, 13, 0, EXC4K, MMU4K, 4, 0, 48, 4,15,0,0,15,0,0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? linesize? etc */ \
{ "RM5200", MIPS_RM5200,0xa0, 0, EXC4K, MMU4K, 4, 0, 48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \
{ "RM7000", MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 0, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* instrs/cycle? cachelinesize & assoc.? RM7000A? */ \
{ "RM7900", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 0, 64, 4,14,5,1,14,5,1,18, 6, 1 }, /* instrs/cycle? cachelinesize? assoc = 4ways for all */ \
{ "RM9000", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 0, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* This is totally bogus */ \
{ "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 1, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ "4Kc", 0x100+MIPS_4Kc, 1, 0, EXC32, MMU32, 32, 1, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \
{ "4KEc", 0x100+MIPS_4KEc_R2, 1, 0, EXC32, MMU32, 32, 2, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \
{ "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 1, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \
{ "5KE", 0x100+MIPS_5KE, 1, 0, EXC64, MMU64, 64, 2, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \
{ "24KEc", 0x100+MIPS_24KE, 1, 0, EXC32, MMU32, 32, 2, 32, 4,15,5,2,15,5,2, 0, 0, 0 }, /* revision level? DCOUNT? instrs/cycle? cache? BOGUS, TODO */ \
{ "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
{ "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 1, 32, 2,13,4,1,12,4,1, 0, 0, 0 }, /* 2ways I, 2ways D */ \
{ "AU1000", 0x00302, 0x01, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \
{ "AU1500", 0x10302, 0x02, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,4,14,5,4, 0, 0, 0 }, \
{ "AU1100", 0x20302, 0x01, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \
{ "SB1", 0x000401, 0x00, 0, EXC64, MMU64, 64, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
{ "SR7100", 0x000504, 0x00, 0, EXC64, MMU64, 64, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \
{ "Allegrex", 0x000000, 0x00, 0, EXC32, MMU32, 2, 0, 4, 1,14,6,2,14,6,2, 0, 0, 0 }, \
{ NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
MIPS_R4600
#define MIPS_R4600
Definition: mips_cpuregs.h:712
MIPS_TX7900
#define MIPS_TX7900
Definition: mips_cpuregs.h:725
MIPS_5KE
#define MIPS_5KE
Definition: mips_cpuregs.h:765
MIPS_R8000
#define MIPS_R8000
Definition: mips_cpuregs.h:710
MIPS_R4000
#define MIPS_R4000
Definition: mips_cpuregs.h:700
MIPS_R4300
#define MIPS_R4300
Definition: mips_cpuregs.h:706
MIPS_RM7000
#define MIPS_RM7000
Definition: mips_cpuregs.h:720
EXC4K
#define EXC4K
Definition: mips_cpu_types.h:40
MIPS_R4200
#define MIPS_R4200
Definition: mips_cpuregs.h:705
MIPS_RC32300
#define MIPS_RC32300
Definition: mips_cpuregs.h:711
EXC3K
#define EXC3K
Definition: mips_cpu_types.h:39
MIPS_R5900
#define MIPS_R5900
Definition: mips_cpuregs.h:723
MMU10K
#define MMU10K
Definition: mips_cpu_types.h:47
MMU64
#define MMU64
Definition: mips_cpu_types.h:49
MIPS_TX3900
#define MIPS_TX3900
Definition: mips_cpuregs.h:716
MIPS_RM5200
#define MIPS_RM5200
Definition: mips_cpuregs.h:721
MIPS_R12000
#define MIPS_R12000
Definition: mips_cpuregs.h:708
EXC64
#define EXC64
Definition: mips_cpu_types.h:42
MIPS_R10000
#define MIPS_R10000
Definition: mips_cpuregs.h:704
MIPS_R4100
#define MIPS_R4100
Definition: mips_cpuregs.h:707
MIPS_R4650
#define MIPS_R4650
Definition: mips_cpuregs.h:715
MIPS_4KEc_R2
#define MIPS_4KEc_R2
Definition: mips_cpuregs.h:766
MIPS_R6000
#define MIPS_R6000
Definition: mips_cpuregs.h:699
MIPS_5Kc
#define MIPS_5Kc
Definition: mips_cpuregs.h:757
MIPS_24KE
#define MIPS_24KE
Definition: mips_cpuregs.h:771
DCOUNT
#define DCOUNT
Definition: mips_cpu_types.h:53
MIPS_R5400
#define MIPS_R5400
Definition: mips_cpuregs.h:726
MMU32
#define MMU32
Definition: mips_cpu_types.h:48
MIPS_R5000
#define MIPS_R5000
Definition: mips_cpuregs.h:717
EXC32
#define EXC32
Definition: mips_cpu_types.h:41
MIPS_R14000
#define MIPS_R14000
Definition: mips_cpuregs.h:709
MIPS_R3000
#define MIPS_R3000
Definition: mips_cpuregs.h:698
MIPS_R2000
#define MIPS_R2000
Definition: mips_cpuregs.h:697
MIPS_4Kc
#define MIPS_4Kc
Definition: mips_cpuregs.h:756
MIPS_R4700
#define MIPS_R4700
Definition: mips_cpuregs.h:713
MMU3K
#define MMU3K
Definition: mips_cpu_types.h:44
NOLLSC
#define NOLLSC
Definition: mips_cpu_types.h:52
MMU4K
#define MMU4K
Definition: mips_cpu_types.h:45
NOFPU
#define NOFPU
Definition: mips_cpu_types.h:54
MMU8K
#define MMU8K
Definition: mips_cpu_types.h:46

Definition at line 67 of file mips_cpu_types.h.

Referenced by mips_cpu_list_available_types(), and mips_cpu_new().

◆ MMU10K

#define MMU10K   10

Definition at line 47 of file mips_cpu_types.h.

Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_new(), and X().

◆ MMU32

#define MMU32   32

Definition at line 48 of file mips_cpu_types.h.

Referenced by mips_cpu_tlbdump().

◆ MMU3K

#define MMU3K   3

Definition at line 44 of file mips_cpu_types.h.

Referenced by coproc_register_write(), coproc_tlbpr(), coproc_tlbwri(), MEMORY_RW(), mips_coproc_tlb_set_entry(), mips_cpu_new(), and mips_cpu_tlbdump().

◆ MMU4K

#define MMU4K   4

Definition at line 45 of file mips_cpu_types.h.

Referenced by coproc_register_write().

◆ MMU64

#define MMU64   64

Definition at line 49 of file mips_cpu_types.h.

◆ MMU8K

#define MMU8K   8

Definition at line 46 of file mips_cpu_types.h.

Referenced by mips_cpu_new().

◆ NOFPU

#define NOFPU   4

Definition at line 54 of file mips_cpu_types.h.

Referenced by coproc_function(), and X().

◆ NOLLSC

#define NOLLSC   1

Definition at line 52 of file mips_cpu_types.h.

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